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7-bit, programmable, dual-phase, mobile, cpu, synchronous buck controller ADP3208A ?2008 scillc. all rights reserved. publication order number: january 2008 C rev. 2 ADP3208A/d features single-chip solution fully compatible with the intel? imvp-6+? specifications integrated mosfet drivers selectable 1- or 2-phase operation with up to 1 mhz per phase switching frequency guaranteed 8 mv worst-case differentially sensed core voltage error over temperature automatic power-saving mode maximizes efficiency with light load during deeper sleep operation soft transient control reduces inrush current and audio noise active current balancing between output phases independent current limit and load line setting inputs for additional design flexibility built-in power good blanking supports voltage identification (vid) on-the-fly transients 7-bit, digitally programmable dac with 0.3 v to 1.5 v output short-circuit protection with programmable latch-off delay clock enable output delays the cpu clock until the core voltage is stable output power or current monitor options 48-lead lfcsp ADP3208A version has 1.0v boot voltage applications notebook power supplies for next-generation intel processors general description the adp3208 is a highly efficient, multiphase, synchronous buck switching regulator controller. with its integrated drivers, the adp3208 is optimized for converting the notebook battery voltage into the core supply voltage required by high performance intel processors. an internal 7-bit dac is used to read a vid code directly from the processor and to set the cpu core voltage to a value within the range of 0.3 v to 1.5 v. the phase relationship of the output signals ensures interleaved 2-phase operation. the adp3208 uses a multimode architecture run at a program- mable switching frequency and optimized for efficiency depending on the output current requirement. the adp3208 switches between single- and dual-phase operation to maximize efficiency with all load conditions. the chip includes a programmable load line slope function to adjust the output voltage as a function of the load current so that the core voltage is always optimally positioned for a load transient. the adp3208 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output. the ic supports on-the-fly output voltage changes requested by the cpu. adp3208 is specified over the extended commercial temperature range of 0c to 100c and is available in a 48-lead lfcsp functional block diagram rt drvh2 bst2 sw2 drvl2 pgnd2 pvcc2 drv2 in od2 drvh1 bst1 sw1 drvl1 pgnd1 pvcc1 drv1 in od1a od1b v rp m rp m ramp sp oscillator pwm cmps pwm latch phase control psi vdac vref fbrtn st varfreq dprslp dprstp vdac spsel ss pwrgd pgdelay clken en vcc bias gnd refth bias uvth ovth switch amps comp fb err amp ss lline cscomp csref cssum csamp clim cmp clref clthsel clim vrtt ttsns fbrtn vcc adp3208 uvlo ref pmon pwm pmon pmonfs csavg vref ramp gener- ator refer- ence select vid dac house- keeping vid6, vid5, vid4, vid3, vid2, vid1, vid0 psi ? ? ? + + + + ? ? + ? + ? + ? + ? + + ? 06374-001 figure 1.
ADP3208A rev. 2 | page 2 of 38 | www.onsemi.com table of contents features...............................................................................................1 applications .......................................................................................1 general description..........................................................................1 functional block diagram...............................................................1 revision history................................................................................2 specifications .....................................................................................3 timing diagram................................................................................7 absolute maximum ratings ............................................................8 esd caution ..................................................................................8 pin configuration and function descriptions .............................9 test circuits .....................................................................................11 typical performance characteristics............................................12 theory of operation.......................................................................15 number of phases .......................................................................15 operation modes ........................................................................15 differential sensing of output voltage ....................................18 output current sensing .............................................................18 active impedance control mode .............................................18 current control mode and thermal balance.........................19 voltage control mode ................................................................19 power good monitoring ............................................................19 power-up sequence and soft start ...........................................19 soft transient...............................................................................20 current limit, short-circuit, and latch-off protection.......20 changing vid on the fly...........................................................21 output crowbar ..........................................................................23 reverse voltage protection........................................................23 output enable and uvlo.........................................................23 thermal throttling control......................................................23 power monitor function ...........................................................24 application information ................................................................27 setting the clock frequency for pwm....................................27 setting the switching frequency for rpm operation of phase 1 ........................................................27 soft start and current limit latch-off delay times ............27 pwrgd delay timer ................................................................28 inductor selection.......................................................................28 c out selection..............................................................................30 power mosfets .........................................................................31 ramp resistor selection ............................................................32 comp pin ramp ........................................................................32 current limit setpoint...............................................................32 power monitor ............................................................................33 feedback loop compensation design ....................................33 c in selection and input current di/dt reduction ..................34 soft transient setting .................................................................34 selecting thermal monitor components................................34 tuning procedure for adp3208 ...............................................35 layout and component placement..........................................36 outline dimension .........................................................................38 ordering guide ...........................................................................38 revision history 01/08rev 2: conversion to on semiconductor 08/07rev sp1: changed to ADP3208A 10/05rev sp0: initial version
ADP3208A rev. 2 | page 3 of 38 | www.onsemi.com specifications vcc = pvcc1 = pvcc2 = bst1 = bst2 = high = 5 v, fbrtn = gnd = sw1 = sw2 = pgnd1 = pgnd2 = low = 0 v, en = varfreq = high, dprslp = 0 v, psi = 1.05 v, dprstp = 0 v, v vid = 1.2000 v, t a = 0c to 100c, unless otherwise noted. 1 current entering a pin (sunk by the device) has a positive sign. table 1. parameter symbol conditions min typ max unit voltage error amplifier output voltage range v comp 0.8 3.6 v dc accuracy v fb relative to nominal v vid , lline = csref v vid = 0.5000 v to 1.5000 v ?8 +8 mv v vid = 0.3000 v to 0.4875 v ?10 +10 mv boot voltage v boot(fb) start-up 0.992 1.0 1.008 v lline positioning accuracy v fb lline ? csref = ?80 mv 78 80 82 mv lline ? csref = ?200 mv 180 200 220 mv lline input bias current i lline ?80 +80 na differential nonlinearity 2 ?1 +1 lsb line regulation v fb vcc = 4.75 v to 5.25 v 0.005 % input bias current i fb ?1 +1 a fbrtn current i fbrtn 60 400 a output current i comp fb forced to v vid ? 3% ?4 ma fb forced to v vid + 3% 900 a gain bandwidth product 2 gbw comp = fb 20 mhz slew rate 2 c comp = 10 pf 25 v/ s vid dac inputs input low voltage v il vid(x) 0.52 0.3 v input high voltage v ih vid(x) 0.7 0.52 v input current i in(vid) sink current 1 a vid transition delay time 2 vid code change to fb change 400 ns pwm oscillator frequency range 2 psi = dprstp = 1.05 v, dprslp = 0 v 0.3 3 mhz frequency f osc t a = 25c, rt = 250 k, pwm mode, varfreq = high, v vid = 1.5000 v 400 khz t a = 25c, rt = 125 k, pwm mode, varfreq = high, v vid = 1.5000 v 750 khz rt voltage v rt rt = 250 k to gnd, v vid = 1.5000 v 1.08 1.25 1.32 v varfreq = low vrpm reference voltage v vrpm i vrpm = 0 0.95 1 1.05 v i vrpm = 120 a 0.95 1 1.16 v rpm output current i rpm v vid = 1.5000 v, rt = 250 k ?5 a rpm comparator offset v os(rpm) |v comp ? v rpm |, psi = 0 v ?20 ?1 +15 mv ramp input voltage v ramp 0.9 1.0 1.1 v ramp input current range i ramp en = high 1 50 a ramp input current in shutdown en = low or uvlo, ramp = 19 v 1 a current sense amplifier offset voltage v os(csa) cssum ? csref ?2.0 +2.0 mv input bias current i cssum ?65 +65 na input common-mode range 2 cssum and csref 0 3.5 v output voltage range v cscomp 0.05 2.7 v output current i cscomp sink current 1 ma source current ?15 ma
ADP3208A rev. 2 | page 4 of 38 | www.onsemi.com parameter symbol conditions min typ max unit gain bandwidth product 2 gbw csa 10 mhz slew rate 2 c cscomp = 10 pf 10 v/ s current balance amplifier common-mode voltage range 2 v sw(x) ?600 +200 mv input resistance r sw(x) 30 50 60 k input current i sw(x) sw(x) = 0 v ?3.5 a input current matching i sw(x) sw(x) = 0 v ?5 +5 % zero current switching threshold voltage v zcs(sw1) dprslp = 3.3 v, dcm ?6 mv dcm minimum off time masking t offmask dprslp = 3.3 v, sw1 falling 450 ns current limit comparator output current i clim r clim = 125 k 10 a current limit threshold voltage v clth v csref ? v cscomp , r clim = 125 k, sp = low (2-phase), psi = 1.05 v 111 125 139 mv v csref ? v cscomp , r clim = 125 k, sp = low (2-phase), psi = 0 v or dprslp = low 54 62.5 74 mv v csref ? v cscomp , r clim = 125 k, sp = high (1-phase) 111 125 139 mv current limit setting ratio v cl /v ilim , psi = 1.05 v 0.1 v cl /v ilim , psi = low, sp = low 0.05 soft start/latch-off timer output current i ss v ss < 1.7 v, start-up ?10 ?8 ?6 a v ss > 1.7 v, normal mode ?48 a v ss > 1.7 v, current limit ?2.5 ?2 ?1.5 a termination threshold voltage v th(ss) start-up, ss rising 1.6 1.7 1.8 v normal mode operating voltage clken = low 2.9 v current limit latch-off voltage v loff(ss) current limit or pwrgd failure, ss falling 1.55 1.65 1.8 v soft transient control st sourcing current i source(st) fast exit from deeper sleep mode, dprslp = 0 v, st = v dac ? 0.3 v ?9 a slow exit from deeper sleep mode, dprslp = 3.3 v, dprstp = 0, st = v dac ? 0.3 v ?2.5 a st sinking current i sink(st) slow entry to deeper sleep, dprslp = 3.3 v, st = v dac + 0.3 v 2.5 a st offset voltage v os(st) |st ? v vid | at the end of pwrgd masking ?25 +25 mv minimum capacitance 2 c st 100 pf extended pwrgd masking comparator voltage threshold v th(st) |st ? v vid |, dprslp = 3.3 v, st falling 170 mv digital control inputs input low voltage v il psi , dprstp 0.3 v varfreq, sp 0.7 v dprslp, en 1.0 v input high voltage v ih psi , dprstp 0.7 v varfreq, sp 4 v dprslp, en 2.3 v input current i in dprstp , varfreq, dprslp, sp 20 na en = low or en = high 20 na en = v th(en) , high-to-low or low-to-high transition 60 a
ADP3208A rev. 2 | page 5 of 38 | www.onsemi.com parameter symbol conditions min typ max unit dprstp = high, psi = high 1 a psi = low ?100 na thermal throttling/crowbar disable control ttsns voltage range 2 temperature sensing 0.4 5 v crowbar disable threshold disable 0 50 mv ttsns vrtt threshold voltage v vrtt(ttsns) vcc = 5 v, ttsns falling 2.45 2.5 2.55 v ttsns vrtt threshold hysteresis 50 95 mv ttsns crowbar disable threshold voltage v cbdis(ttsns) 50 mv ttsns input current ttsns > 1.0 v, temperature sensing ?1 +1 a ttsns = 0 v, disabling overvoltage protection ?3 a vrtt output low voltage v ol(vrtt) i sink(vrtt) = 400 a 50 100 mv vrtt output high voltage v oh(vrtt) i source(vrtt) = ?400 a 4 5 v power good csref undervoltage threshold v uv(csref) relative to v vid = 0.5 v to 1.5 v ?300 mv relative to v vid = 0.3125 v to 0.4875 v ?160 mv csref overvoltage threshold v ov(csref) relative to v vid = 0.5 v to 1.5 v 150 200 250 mv csref crowbar (overvoltage protection) threshold v cb(csref) relative to fbrtn 1.65 1.7 1.75 v csref reverse voltage detection threshold v rvp(csref) relative to fbrtn csref falling ?400 ?300 mv csref rising ?60 ?5 mv pwrgd output low voltage v ol(pwrgd) i sink(pwrgd) = 4 ma 70 200 mv pwrgd output leakage current v pwrdg = 5 v 0.03 3 a power good delay timer pgdelay voltage detection threshold v th(pgdelay) 2.9 v pgdelay charge current i pgdelay v pgdelay = 2.0 v ?3 a pgdelay discharge resistance r pgdelay v pgdelay = 0.2 v 600 pwrgd masking time 130 s clock enable output low voltage i sink = 4 ma 100 400 mv output leakage current clken = 5 v, v ss = gnd 1 a power monitor pmon output resistance i sink = 2 ma 16 pmon leakage current pmon = 5 v 1 a pmon oscillator frequency pmonfs = 2 v 320 khz pmonfs voltage range 2 1.5 4 v pmonfs output current pmonfs = 2.5 v ?10 a high-side mosfet drivers drvh output resistance, sourcing current bst ? sw = 4.6 v 1.9 3.3 drvh output resistance, sinking current bst ? sw = 4.6 v 1.5 3 transition times tr drvh, bst ? sw = 4.6 v, c l = 3 nf, see figure 2 10 30 ns tf drvh bst ? sw = 4.6 v, c l = 3 nf, see figure 2 8 25 ns propagation delay time tpdh drvh bst ? sw = 4.6 v, see figure 2 16 70 ns bst quiescent current en = low, shutdown 5 a
ADP3208A rev. 2 | page 6 of 38 | www.onsemi.com parameter symbol conditions min typ max unit en = high, no switching 120 a low-side mosfet drivers output resistance, sourcing current 1.8 3.3 output resistance, sinking current 1.4 2.5 transition times tr drvl c l = 3 nf, see figure 2 11 30 ns tf drvl c l = 3 nf, see figure 2 9 25 ns propagation delay time tpdl drvl c l = 3 nf, see figure 2 13 30 ns sw transition timeout t to(sw) bst ? sw = 4.6 v 80 130 300 ns zero voltage switching detection threshold v zvs(sw) 2.2 v pvcc quiescent current en = low, shutdown 13 a en = high, no switching 180 a supply supply voltage range 2 v cc 4.5 5.5 v supply current en = high, normal mode 5.5 10 ma en = low, shutdown 32 150 a vcc ok threshold voltage v ccok vcc rising 4.4 4.5 v vcc uvlo threshold voltage v ccuvlo vcc falling 4.0 4.2 v uvlo hysteresis 2 150 mv 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2 guaranteed by design or characterization, not production tested.
ADP3208A rev. 2 | page 7 of 38 | www.onsemi.com timing diagram timing is referenced to the 90% and 10% points, unless otherwise noted. in drvh (with respect to sw) drvl sw tpdl drvl tf drvl tr drvl tpdl drvh tf drvh tpdh drvh tr drvh v th v th 1v tpdh drvl 06374-006 figure 2. timing diagram
ADP3208A rev. 2 | page 8 of 38 | www.onsemi.com absolute maximum ratings table 2. parameter rating vcc, pvcc1, pvcc2 ?0.3 v to +6 v fbrtn, pgnd1, pgnd2 ?0.3 v to +0.3 v bst1, bst2 dc ?0.3 v to +25 v t < 200 ns ?0.3 v to +30 v bst1 to sw1, bst2 to sw2 ?0.3 v to +6 v drvh1, drvh2, sw1, sw2 dc ?5 v to +20 v t < 200 ns ?10 v to +25 v drvh1 to sw1, drvh2 to sw2, ?0.3 v to +6 v drvl1 to pgnd1, drvl2 to pgnd2 dc -0.3 v to +6 v t < 200 ns -5v to +6v ramp (in shutdown) dc ?0.3 v to +20 v t < 200 ns ?0.3 v to +25 v all other inputs and outputs ?0.3 v to +6 v storage temperature ?65c to +150c operating ambient temperature range 0c to 100c operating junction temperature 125c thermal impedance ( ja ) 2-layer board 40c/w lead temperature soldering (10 sec) 300c infrared (15 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADP3208A rev. 2 | page 9 of 38 | www.onsemi.com pin configuration and function descriptions 13 14 15 16 17 18 19 20 21 22 23 24 pmon pmonfs clim lline cscomp csref cssum ramp vrpm rpm rt gnd 48 47 46 45 44 43 42 41 40 39 38 37 dprslp dprstp psi vid0 vid1 vid2 vid3 vid4 vid5 vid6 sp vcc 1 2 3 4 5 6 7 8 9 10 11 12 en pwrgd pgdelay clken fbrtn fb comp ss st varfreq vrtt ttsns drvh1 sw1 pvcc1 drvl1 pgnd1 pgnd2 drvl2 pvcc2 sw2 drvh2 bst2 35 bst1 36 34 33 32 31 30 29 28 27 26 25 adp3208 top view (not to scale) pin 1 indicator 06374-002 figure 3. lfcsp pin configuration table 3. pin function descriptions pin no. mnemonic description 1 en enable input. driving the pin low shuts down the chip, disables the driver outputs, pulls pwrgd and vrtt low, and pulls clken high. 2 pwrgd power good output. open-drain output. a low logic state means that the output voltage is outside of the vid dac defined range. 3 pgdelay power good delay setting input/output. a capacitor connected from this pin to gnd sets the power good delay time. 4 clken clock enable output. open-drain output. a low logic stat e enables the cpu internal pll clock to lock to the external clock. 5 fbrtn feedback return input/output. this pin remotely sens es the cpu core voltage. it is also used as the ground return for the vid dac and the voltage error amplifier blocks. 6 fb voltage error amplifier feedback input. the inverting input of the voltage error amplifier. 7 comp voltage error amplifier output and frequency compensation point. 8 ss soft start and latch-off delay setting input/output. an ex ternal capacitor from this pi n to gnd sets the soft start ramp-up time and the current limit latch-off delay ramp-down time. 9 st soft transient slew rate timing input/output. a capacito r from this pin to gnd sets the slew rate of the output voltage when it transitions from one vid setting to another, including boot-to-active vid, vid on the fly, and deeper sleep entry and exit transients. 10 varfreq variable frequency enable input. a high logic state enables the pwm clock frequency to vary with vid code. 11 vrtt voltage regulator thermal throttling output. logic high state indicates that the voltage regulator temperature at the remote sensing point exceeded a set alarm threshold level. 12 ttsns thermal throttling sense and crowbar disable input. a resistor divider where the upper resistor is connected to vcc, the lower resistor (ntc thermistor) is connected to gnd, and the center point is connected to this pin and acts as a temperature sensor half bridge. connecting ttsns to gnd disables the thermal throttling function and disables the crowbar, or overvoltage protection (ovp), feature of the chip. 13 pmon power monitor output. open-drain output. a pull-up resistor from pmon to csref provides a duty cycle modulated power output signal. an external rc network ca n be used to convert the digital signal stream to an averaged power analog output voltage. 14 pmonfs power monitor full-scale setting input/output. a resist or from this pin to gnd sets the full-scale value of the pmon output signal. 15 clim current limit setting input/output. an external resistor from this pin to gnd sets the current limit threshold of the converter.
ADP3208A rev. 2 | page 10 of 38 | www.onsemi.com pin no. mnemonic description 16 lline load line programming input. the center point of a resistor divider connected between csref and cssum can be tied to this pin to set the load line slope. 17 cscomp current sense amplifier output and frequency compensation point. 18 csref current sense reference input. this pin must be co nnected to the common point of the output inductors. the node is shorted to gnd through an internal switch when the chip is disabled to provide soft stop transient control of the converter output voltage. 19 cssum current sense summing input. external resistors from ea ch switch node to this pin sum the inductor currents to provide total current information. 20 ramp pwm ramp slope setting input. an external resistor from the converter input voltage node to this pin sets the slope of the internal pwm stabilizing ramp used for phase-current balancing. 21 vrpm rpm mode reference voltage output. 22 rpm ramp pulse modulation current source output. a resi stor between this pin and vrpm sets the rpm comparator upper threshold. 23 rt pwm oscillator frequency setting input. an external resistor from this pin to gnd sets the pwm oscillator frequency. 24 gnd analog and digital signal ground. 25 bst2 high-side bootstrap supply for phase 2. a capacitor from this pin to sw2 holds the bootstrapped voltage while the high-side mosfet is on. 26 drvh2 high-side gate drive output for phase 2. 27 sw2 current balance input for phase 2 and current return for high-side gate drive. 28 pvcc2 power supply input/output of low-side gate driver for phase 2. 29 drvl2 low-side gate drive output for phase 2. 30 pgnd2 low-side driver power ground for phase 2. 31 pgnd1 low-side driver power ground for phase 1. 32 drvl1 low-side gate drive output for phase 1. 33 pvcc1 power supply input/output of low-side gate driver for phase 1. 34 sw1 current balance input for phase 1 and current return for high-side gate drive. 35 drvh1 high-side gate drive output for phase 1. 36 bst1 high-side bootstrap supply for phase 1. a capacitor from this pin to sw1 holds the bootstrapped voltage while the high-side mosfet is on. 37 vcc power supply input/output of the controller. 38 sp single-phase select input. logic high state sets single-phase configuration. 39 to 45 vid6 to vid0 voltage identification dac inputs. a 7-bit word (the vid code) programs the dac output voltage, the reference voltage of the voltage error amplifier without a load (see the vid code table, table 6). 46 psi power state indicator input. driving this pin low forces the controller to operate in single-phase mode. 47 dprstp deeper stop control input. the logic state of this pin is usually complementary to the state of the dprslp pin; however, during slow deeper sleep exit, both pins are logic low. 48 dprslp deeper sleep control input.
ADP3208A rev. 2 | page 11 of 38 | www.onsemi.com test circuits 7-bit code 1 f 10nf 100nf 5v 20k ? 250k ? 1k ? 100nf adp3208 48 1 1.05v en pwrgd pgdelay clken fbrtn fb comp ss st varfreq vrtt ttsns pmon pmonfs clim lline cscomp csref cssum ramp vrpm rpm rt gnd dprslp dprstp psi vid0 vid1 vid2 vid3 vid4 vid5 vid6 sp vcc bst1 sw1 pvcc1 drvl1 pgnd1 pgnd2 drvl2 pvcc2 sw2 drvh2 bst2 06374-003 figure 4. closed-loop output voltage accuracy cssum 17 cscomp 19 37 vcc csref 18 gnd 24 3 9k ? 100nf 1k ? 1v adp3208 v os = cscomp ? 1v 40 06374-004 5v figure 5. current sense amplifier, v os 37 vcc 10k ? v 1v adp3208 v fb = fb v = 80mv ? fb v= 0mv + ? 7 comp 6 fb 16 lline 18 csref 24 gnd vid dac 06374-005 5v figure 6. positioning accuracy
ADP3208A rev. 2 | page 12 of 38 | www.onsemi.com typical performance characteristics v vid = 1.5 v, t a = 20c to 100c, unless otherwise noted. 95 85 90 80 75 70 65 60 55 50 0 10203040 06374-007 load current (a) efficiency (%) v in = 8v v in = 19v v in = 12v f sw = 318khz figure 7. pwm mode efficiency vs. load current 95 60 030 06374-008 load current (a) efficiency (%) 90 85 80 75 70 65 10 20 v in = 8v v in = 19v v in = 12v figure 8. rpm mode efficiency vs. load current in ccm only 91 75 030 06374-009 load current (a) efficiency (%) 89 87 85 83 81 79 77 10 20 v in = 8v ccm/dcm transition v in = 19v v in = 12v figure 9. rpm mode efficiency vs. load current automatic in ccm/dcm 90 70 0 06374-010 load current (a) efficiency (%) 88 86 84 82 80 78 76 74 72 10 20 30 40 pwm v in = 12v rpm automatic ccm/dcm rpm ccm only figure 10. efficiency vs. load current in all modes 400 0 030 06374-011 load current (a) switching frequency (khz) 350 300 250 200 150 100 50 5 10152025 ccm only automatic ccm/dcm figure 11. switching frequency vs. load current in rpm 500 0 01.50 06374-012 vid output voltage (v) switching frequency (khz) 400 300 200 100 0.25 0.50 0.75 1.00 1.25 rt = 237k ? varfreq = 0v varfreq = 5v figure 12. switching frequency vs. vid output voltage in pwm
ADP3208A rev. 2 | page 13 of 38 | www.onsemi.com 350 0 01.5 06374-013 output voltage (v) switching frequency (khz) 300 250 200 150 100 50 0.5 1.0 rt = 237k ? rpm = 80.5k ? figure 13. switching frequency vs. output voltage in rpm 1200 0 080 06374-014 output power (w) pmon voltage (mv) 1000 800 600 400 200 20 40 60 figure 14. pmon voltage vs. output power 10000 10 10 10000 06374-015 rt (k ? ) switching frequency (khz) 100 1000 100 1000 vid = 1.2v vid = 1.5v vid = 0.675v figure 15. per phase switching frequency vs. rt resistor 1.54 1.36 050 06374-016 load current (a) efficiency (%) 1.52 1.50 1.48 1.46 1.44 1.42 1.40 1.38 10 20 30 40 +2% ?2% measured load line specified load line figure 16. load line accuracy 180 0 06 06374-017 vcc voltage (v) vcc current ( a) 160 140 120 100 80 60 40 20 24 v in = 12v en = low figure 17. vcc current vs. vcc voltage with enable low ss 06374-018 ch1 2.00v ch3 2.00v ch2 1.00v ch4 1.00v m2.00ms a ch4 740mv t 13.60% 3 2 clken pwrgd output voltage figure 18. start-up waveforms
ADP3208A rev. 2 | page 14 of 38 | www.onsemi.com 06374-019 ch1 10.0v ch3 5.00a ref1 10.0v 1.00 s ch2 5.00a ch4 20.0mv a ch3 8.00a m1.00 s t 20.00% 1 r1 2 4 output voltage l2 current l1 current switch node 1 switch node 2 figure 19. dual-phase, interleaved pwm waveform, 20 a load 06374-020 ch4 50.0mv m40.0 s a ch4 1.02v t 14.20% 4 output voltage figure 20. load transient 9 a to 44 a 06374-021 ch4 50.0mv m10.0 s a ch4 1.02v t 14.20% 4 output voltage figure 21. load transient 9 a to 44 a 06374-022 ch1 10.0v ch3 10.0v ch2 1.00v ch4 20.0mv~ m4.00 s a ch2 600mv t 14.40% 4 3 2 1 switch node 2 switch node 1 output voltage psi figure 22. psi transition 06374-023 ch4 10.0mv m1.00 s a ch4 2.00mv t 10.40% 4 output voltage figure 23. pwm mode output ripple, 40 a load, v in = 12 v
ADP3208A rev. 2 | page 15 of 38 | www.onsemi.com theory of operation the adp3208 combines multimode pulse width modulated (pwm) control and ramp pulse modulated (rpm) control with multiphase logic outputs for use in single- and dual-phase synchronous buck cpu core supply power converters. the internal 7-bit vid dac conforms to the intel imvp-6+ specifications. multiphase operation is important for producing the high currents and low voltages demanded by todays microprocessors. handling high currents in a single-phase converter would put too high of a thermal stress on system components such as the inductors and mosfets. the multimode control of the adp3208 is a stable, high performance architecture that includes ? current and thermal balance between phases ? high speed response at the lowest possible switching frequency and minimal count of output decoupling capacitors ? minimized thermal switching losses due to lower frequency operation ? high accuracy load line regulation ? high current output by supporting 2-phase operation ? reduced output ripple due to multiphase ripple cancellation ? high power conversion efficiency with heavy and light loads ? increased immunity from noise introduced by pc board layout constraints ? ease of use due to independent component selection ? flexibility in design by allowing optimization for either low cost or high performance number of phases the number of operational phases can be set by the user. tying the sp pin to the vcc pin forces the chip into single-phase operation; otherwise, dual-phase operation is automatically selected and the chip switches between single- and dual-phase modes as the load changes to optimize power conversion efficiency. in dual-phase configuration, sp is low and the timing relationship between the two phases is determined by internal circuitry that monitors the pwm outputs. because each phase is monitored independently, operation approaching 100% duty cycle is possible. in addition, more than one output can be active at a time, permitting overlapping phases. operation modes the number of phases can be static (see the number of phases section) or dynamically controlled by system signals to optimize the power conversion efficiency with heavy and light loads. if sp is set low (user-selected dual-phase mode) during a vid transient or with a heavy load condition (indicated by dprslp being low and psi being high), the adp3208 runs in 2-phase, interleaved pwm mode to achieve minimal v core output voltage ripple and the best transient performance possible. if the load becomes light (indicated by psi being low or dprslp being high), adp3208 switches to single -phase mode to maximize the power conversion efficiency. in addition to changing the nu mber of phases, the adp3208 is also capable of dynamically changing the control method. in dual-phase operation, the ad p3208 runs in pwm mode, where the switching frequency is controlled by the master clock. in single-phase operation (commanded by the psi low state), the adp3208 runs in rpm mode, where the switching frequency is controlled by the ripple voltage appearing on the comp pin. in rpm mode, the drvh1 pin is driven high each time the comp pin voltage rises to a voltage limit set by the vid voltage and an external resistor connected between the vrpm and rpm pins. if the device is in single-phase mode and the system signal dprslp is asserted high during the deeper sleep mode of cpu operation, the adp3208 continues running in rpm mode but offers the option of turning off the low-side (synchronous rectifier) mosfet when the inductor current drops to 0. turning off the low-side mosfets at the zero current crossing prevents reversed inductor current build up and breaks synchronous operation of high- and low-side switches. due to the asynchronous operation, the switching frequency becomes slower as the load current decreases, resulting in good power conversion efficiency with very light loads. table 4 summarizes how the adp3208 dynamically changes the number of active phases and transitions the operation mode based on system signals and operating conditions.
ADP3208A rev. 2 | page 16 of 38 | www.onsemi.com table 4. phase number and operation modes 1 psi no. dprslp vid transition 2 current limit no. of phases selected by the user no. of phases in operation operation modes 3 * * yes * n [2 or 1] n pwm, ccm only 1 0 no * n [2 or 1] n pwm, ccm only 0 0 no no * 1 rpm, ccm only 0 0 no yes * 1 pwm, ccm only * 1 no no * 1 rpm, automatic ccm/dcm * 1 no yes * 1 pwm, ccm only 1 * = dont care. 2 vid transient period is the time following any vid change, including entry into and exit from deeper sleep mode. the duration of vid transient period is the same as that of pwrgd masking time. 3 ccm stands for continuous current mode, and dcm stands for discontinuous current mode. i r = a r i ramp q s rd flip-flop 1v q s rd flip-flop r a c fb r fb c a c b vdc v cs r cs c cs r ph r ph drvh drvl gate driver sw vcc l r i l r i load comp fb fbrtn cscomp cssum csref drvl1 sw1 drvh1 c r vrmp bst bst1 5v drvh drvl gate driver sw vcc drvl2 sw2 drvh2 bst bst2 5v q 400ns q r2 r1 r1 r2 1v 30mv in dcm lline in dcm +? + ? + + 06374-024 figure 24. single-phase rpm mode
ADP3208A rev. 2 | page 17 of 38 | www.onsemi.com i r = a r i ramp a d 0.2v clock oscillator q s rd flip-flop i r = a r i ramp a d 0.2v clock oscillator q s rd flip-flop v cc l r i l r i load c r c r drvh drvl gate driver sw vcc drvl1 sw1 drvh1 bst bst1 5v in drvh drvl gate driver sw vcc drvl2 sw2 drvh2 bst bst2 5v ramp r a c fb r fb c a c b vdc v cs r cs c cs r ph r ph comp fb fbrtn cscomp cssum csref lline + +? + ? + 06374-025 figure 25. dual-phase pwm mode
ADP3208A rev. 2 | page 18 of 38 | www.onsemi.com setting switch frequency master clock frequency in pwm mode when the adp3208 runs in pwm, the clock frequency of the adp3208 is set by an external resistor connected from the rt pin to gnd. the frequency is constant at a given vid code but varies with the vid voltage: the lower the vid voltage, the lower the clock frequency. the variation of clock frequency with vid voltage maintains constant v core ripple and improves power conversion efficiency at lower vid voltages. figure 15 shows the relationship between clock frequency and vid voltage, parameterized by rt resistance. to determine the switching frequency per phase, divide the clock by the number of phases in use. switching frequency in rpm mode single-phase operation in single-phase rpm mode, the switching frequency is controlled by the ripple voltage on the comp pin, rather than by the master clock. each time the comp pin voltage exceeds the rpm pin voltage threshold level determined by the vid voltage and the external resistor connected between rpm and vrpm, an internal ramp signal is started and drvh1 is driven high. the slew rate of the internal ramp is programmed by the current entering the ramp pin. one-third of the ramp current charges an internal ramp capacitor (5 pf typical) and creates a ramp. when the internal ramp signal intercepts the comp voltage, the drvh1 pin is reset low. in continuous current mode, the switching frequency of rpm operation is almost constant. while in discontinuous current conduction mode, the switching frequency is reduced as a function of the load current. differential sensing of output voltage the adp3208 combines differential sensing with a high accuracy vid dac, referenced by a precision band gap source and a low offset error amplifier, to meet the rigorous accuracy requirement of the intel imvp-6+ specification. in steady-state mode, the combination of the vid dac and error amplifier maintain the output voltage for a worst-case scenario within 8 mv of the full operating output voltage and temperature range. the cpu core output voltage is sensed between the fb and fbrtn pins. fb should be connec ted through a resistor to the positive regulation pointthe vcc remote sensing pin of the microprocessor. fbrtn should be connected directly to the negative remote sensing pointthe v ss sensing point of the cpu. the internal vid dac and precision voltage reference are referenced to fbrtn and have a maximum current of 200 a for guaranteed accurate remote sensing. output current sensing the adp3208 includes a dedicated current sense amplifier (csa) to monitor the total output current of the converter for proper voltage positioning vs. load current and for over current detection. sensing the current delivered to the load is an inherently more accurate method than detecting peak current or sampling the current across a sense element, such as the low- side mosfet. the current sense amplifier can be configured several ways, depending on system optimization objectives, and the current information can be obtained by ? output inductor esr sensing without the use of a thermistor for the lowest cost ? output inductor esr sensing with the use of a thermistor that tracks inductor temperature to improve accuracy ? discrete resistor sensing for the highest accuracy at the positive input of the csa, the csref pin is connected to the output voltage. at the negative input (that is, the cssum pin of the csa), signals from the sensing element (in the case of inductor dcr sensing, signals from the switch node side of the output inductors) are summed together by series summing resistors. the feedback resistor between the cscomp and cssum pins sets the gain of the current sense amplifier, and a filter capacitor is placed in parallel with this resistor. the current information is then given as the voltage difference between the cscomp and csref pins. this signal is used internally as a differential input for the current limit comparator. an additional resistor divider connected between the cscomp and csref pins with the midpoint connected to the lline pin can be used to set the load line required by the microprocessor specification. the current information to set the load line is then given as the voltage difference between the lline and csref pins. this configuration allows the load line slope to be set independently from the current limit threshold. if the current limit threshold and load line do not have to be set independently, the resistor divider between the cscomp and csref pins can be omitted and the cscomp pin can be connected directly to lline. to disable voltage positioning entirely (that is, to set no load line), lline should be tied to csref. to provide the best accuracy for current sensing, the csa has a low offset input voltage and the sensing gain is set by an external resistor ratio. active impedance control mode to control the dynamic output voltage droop as a function of the output current, the signal that is proportional to the total output current, converted from the voltage difference between lline and csref, can be scaled to be equal to the required droop voltage. this droop voltage is calculated by multiplying the droop impedance of the regulator by the output current. this value is used as the control voltage of the pwm regulator. the droop voltage is subtracted from the dac reference output voltage, and the resulting voltage is used as the voltage positioning setpoint. the arrangement results in an enhanced feed-forward response.
ADP3208A rev. 2 | page 19 of 38 | www.onsemi.com current control mode and thermal balance the adp3208 has individual inputs for monitoring the current of each phase. the phase current information is combined with an internal ramp to create a current-balancing feedback system that is optimized for initial current accuracy and dynamic thermal balance. the current balance information is independent from the total inductor current information used for voltage positioning described in the active impedance control mode section. the magnitude of the internal ramp can be set so that the transient response of the sy stem is optimal. the adp3208 monitors the supply voltage to achieve feed-forward control whenever the supply voltage changes. a resistor connected from the power input voltage rail to the ramp pin determines the slope of the internal pwm ramp. more detail about programming the ramp is provided in the application information section. the adp3208 should not requir e external thermal balance circuitry with good layout. however, if mismatch is desired due to uneven cooling in phase, external resistors can be added to individually control phase currents as long as the phase currents are mismatched by less than 30%. if unwanted mismatch exceeds 30%, a new layout that improves phase symmetry should be considered. adp3208 c ramp 20 r sw1 r sw2 switch node 1 switch node 2 vdc r1 r2 reserved for thermal balance tune 06374-027 figure 26. optional current balance resistors in 2-phase operation, alternate cycles of the internal ramp control the duty cycle of the separate phases. figure 26 shows the addition of two resistors from each switch node to the ramp pin; this modifies the ramp-charging current individually for each phase. during phase 1, sw node 1 is high (practically at the input voltage potential) and sw node 2 is low (practically at the ground potential). as a consequence, the ramp pin, through the r2 resistor, sees the tap point of a divider connected to the input voltage, where r sw1 is the upper element and r sw2 is the lower element of the divider. during phase 2, the voltages on sw node 1 and sw node 2 switch and the resistors swap functions. tuning r sw1 and r sw2 allows current to be optimally set for each phase. to increase current for a given phase, decrease r sw for that phase. voltage control mode a high-gain bandwidth error amplifier is used for the voltage mode control loop. the non-inverting input voltage is set via the 7-bit vid dac. the vid codes are listed in table 6. the non-inverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. the output of the error amplifier is the comp pin, which sets the termination voltage of the internal pwm ramps. at the negative input, the fb pin is tied to the output sense location using r b , a resistor for sensing and controlling the output voltage at the remote sensing point. the main loop compensation is incorporated in the feedback network connected between the fb and comp pins. power good monitoring the power good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open-drain output that can be pulled up through an external resistor to a voltage rail not necessarily the same vcc voltage rail that is running the controller. a logic high level indicates that the output voltage is within the voltage limits defined by a range around the vid voltage setting. pwrgd goes low when the output voltage is outside of that range. following the imvp-6+ specification, the pwrgd range is defined to be 300 mv less than and 200 mv greater than the actual vid dac output voltage. for any dac voltage less than 300 mv, only the upper limit of the pwrgd range is monitored. to prevent a false alarm, the power good circuit is masked during various system transitions, including a vid change and entrance into or exit out of deeper sleep. the duration of the pwrgd mask is set to approximately 130 s by an internal timer. if the voltage drop is greater than 200 mv during deeper sleep entry or slow deeper sleep exit, the duration of pwrgd masking is extended by the internal logic circuit. power-up sequence and soft start the power-on ramp-up time of the output voltage is set with a capacitor tied from the ss pin to gnd. the capacitance on the ss pin also determines the current limit latch-off time, as explained in the current limit, short-circuit, and latch-off protection section. the power-up sequence, including the soft start is illustrated in figure 27. in vcc uvlo or shutdown mode, the ss pin is held at zero potential. when vcc ramps to a value greater than the upper uvlo threshold while en is asserted high, the adp3208 enables internal bias and starts a reset cycle of 50 s~60 s. when the initial reset is complete, the chip detects the number of phases set by the user and signals to ramp up the ss voltage. during soft start, the external ss capacitor is charged by an internal 8 a current source. the v core voltage follows the ramping ss voltage up to the v boot voltage level determined by a burnt-in vid code (1.2v according to the imvp-6+ specification). the ADP3208A version has a v boot of 1.0v. all other parameters for the ADP3208A are identical to adp3208. while the v core is regulated at the v boot voltage, the ss capacitor continues to rise. when the ss pin
ADP3208A rev. 2 | page 20 of 38 | www.onsemi.com voltage reaches 1.7 v, the adp3208 immediately asserts the clken signal low if the v core voltage is within the power good range defined by v boot . in addition, the chip reads the vid codes provided by the cpu on the vid [0:6] input pins. the v core voltage changes from the v boot voltage to the vid voltage by a well-controlled soft transition slope (see the soft transient section). during this transition, the ss capacitor is quickly charged up to about a 2.9 v ss clamp level, controlled by the ss source current, which is increased to 48 a (typical). the pwrgd signal is asserted after a t cpu_pwrgd delay of 3 ms~10 ms, as specified by imvp-6+. the power good delay can be programmed by the capacitor connected from the pgdelay pin to gnd. before the clken signal is asserted low, pgdelay is reset to 0. following the assertion of the clken signal, an internal source current of 2 a starts charging up the external capacitor on the pgdelay pin. assuming that the v core voltage has settled within the power good range defined by the vid dac voltage, the pwrgd signal is asserted high when the pgdelay voltage reaches the 2.9 v power good delay termination threshold. vcc = 5v en v ss v boot = 1.2v 1.7v dac and v core clken pwrgd t cpu_pwrgd 06374-028 figure 27. power-up sequence of adp3208 if en is taken low or vcc drops below the vcc uvlo threshold, both the ss capacitor and the pgdelay capacitor are reset to ground to prepare the chip for a subsequent soft start cycle. soft transient the adp3208 provides a soft transient function to reduce inrush current during various transitions, including entrance into and exit out of deeper sleep and the transition from v boot to vid voltage. reducing the inrush current helps decrease the acoustic noise generated by the mlcc input capacitors and inductors. the soft transient feature is implemented with an st buffer amplifier that outputs constant sink or source current on the st pin that is connected to an external capacitor. the capacitor is used to program the slew rate of v core voltage during a vid voltage transient. during steady-state operation, the reference inputs of the voltage error amplifier and the st amplifier are connected to the vid dac output. consequently, the st voltage is a buffered version of vid dac output. when system signals trigger a soft transition, the reference input of the voltage error amplifier switches from the dac output to the st output while the input of the st amplifier remains connected to the dac. the st buffer input recognizes the almost instantaneous vid voltage change and tries to track it. however, tracking is not instantaneous because the slew rate of the buffer is limited by the source and sink current capabilities of the st output. therefore, the v core voltage slew rate is controlled. when the transient period is complete, the reference input of the voltage amplifier reverts to the vid dac output to improve accuracy. table 5 lists the source/sink current on the st pin for various transitions. charging/discharging the external capacitor on the st pin programs the voltage slew rate of the st pin and consequently of the v core output. for example, a 390 pf st capacitor results in a +10 mv/s v core slew rate for fast exit from deeper sleep and a 3.3 mv/s v core slew rate for slow entry into or exit from deeper sleep. table 5. source/sink current of st pin system signals 1 vid transient dprslp dprstp st pin current (a) slow entry into deeper sleep high * ?2.5 fast exit from deeper sleep low * +7.5 slow exit from deeper sleep high high +2.5 transient from v boot to vid * * 2.5 1 * = do not care. current limit, short-circuit, and latch-off protection the adp3208 compares the differential output of a current sense amplifier to a programmable current limit setpoint to provide the current-limiting function. the current limit threshold is set by the user with a resistor connected from the clim pin to gnd, utilizing the fixed (10 a typ) current sourced by the clim pin. the ground-referenced clim voltage is scaled down inside the chip by a factor of 10 in dual-phase operation and by a factor of 20 in single-phase operation. the scaled-down and level-shifted v clth current limit threshold floats on top of the cscomp voltage. the current limit comparator monitors the differential voltage appearing across cscomp and csref and compares it to the floating v clth threshold. if the sensed current exceeds the threshold, a current adp3208: v boot = 1.2v ADP3208A: v boot = 1.0v
ADP3208A rev. 2 | page 21 of 38 | www.onsemi.com limit alert is released and the control of the internal comp voltage is transferred from the voltage error amplifier to the current limit amplifier to maintain an average output current determined by the set current limit level. when the output voltage is less than 200 mv during start-up, a secondary current limit is activated. this is necessary because the voltage swing on the cscomp cannot extend below ground. the secondary current limit circuit clamps the internal comp voltage at around 1.6 v, resulting in duty cycle limited operation. there is also an inherent per phase current limit that protects individual phases in case any of the phases stop functioning due to a faulty component. this limit is based on the maximum normal mode comp voltage. if the output current exceeds the current limit threshold or the output voltage is outside the pwrgd range, the ss pin is discharged by an internal sink current of 2 a. a comparator monitors the ss pin voltage and shuts off the controller when the voltage drops to less than about 1.65 v. because the voltage ramp (2.9 v ? 1.65 v = 1.25 v) and the discharge current (2 a) are internally fixed, the current limit latch-off delay time is determined by the external ss pin capacitor selection. figure 28 shows how the adp3208 re acts to a current overload. 06374-029 3 1 2 4 1ms/div current limit applied latched off switch node 10v/div ss pin 2v/div pwrgd 2v/div output voltage 1v/div figure 28. current overload the controller cycles the phases during the latch-off delay time. if the current overload is removed and the pwrgd is recovered before the 1.65 v threshold is reached, the controller resumes normal operation and the ss pin voltage recovers to a 2.9 v clamp level. the latch off can be reset by either removing and reapplying vcc or by briefly cycling the en pin low and high. to disable the current limit latch-off function, an external pull-up resistor can be tied from the ss pin to the vcc rail. the pull-up current must override the 2 a sink current of the ss pin to prevent the ss capacitor from discharging to a voltage level that is less than the 1.65 v latch-off threshold. changing vid on the fly the adp3208 is designed to tr ack dynamically changing vid code. as a consequence, the cpu vcc voltage can change without the need to reset the controller or the cpu. this concept is commonly referred to as vid on-the-fly (vid otf) transient. a vid otf can occur with either light or heavy load conditions. the processor alerts the controller that a vid change is occurring by changing the vid inputs in lsb incremental steps from the start code to the finish code. the change can be either upwards or downwards steps. when a vid input changes, the adp3208 detects the change but ignores new code for a minimum of 400 ns. this delay is required to prevent the device from reacting to digital signal skew while the 7-bit vid input code is in transition. additionally, the vid change triggers a pwrgd masking timer to prevent a pwrgd failure. each vid change resets and retriggers the internal pwrgd masking timer. as listed in table 6, during a vid transient, the adp3208 forces pwm mode regardless of the state of the system input signals. for example, this means that if the chip is configured as a dual- phase controller but is running in single-phase mode due to a light load condition, a current overload event causes the chip to switch to dual-phase mode to share the excessive load until the delayed current limit latch-off cycle terminates. in user-set single-phase mode, the adp3208 usually runs in rpm mode. when a vid transition occurs, however, the adp3208 switches to dual-phase pwm mode. light load rpm dcm operation in single-phase normal mode, dprslp is pulled low and the apd3208 operates in continuous conduction mode (ccm) over the entire load range. the upper and lower mosfets are always running synchronously and in complementary phase. see figure 29 for the typical waveforms of the adp3208 running in ccm with a 7 a load current. 06374-030 3 1 2 4 400ns/div output voltage 20mv/div inductor current 5a/div switch node 5v/div low-side gate drive 5v/div figure 29. single-phase waveforms in ccm if dprslp is pulled high, the adp3208 operates in rpm mode. if the load condition is light, the chip enters discontinuous con- duction mode (dcm). figure 30 shows a typical single-phase
ADP3208A rev. 2 | page 22 of 38 | www.onsemi.com buck with one upper fet, one lower fet, an output inductor, an output capacitor, and a load resistor. figure 31 shows the path of the inductor current with the upper fet on and the lower fet off. in figure 32 the high-side fet is off and the low- side fet is on. in ccm, if one fet is on, its complementary fet must be off; however, in dcm, both high- and low-side fets are off and no current flows into the inductor (see figure 7 ). figure 34 shows the inductor current and switch node voltage in dcm. in dcm with a light load, the adp3208 monitors the switch node voltage to determine when to turn off the low-side fet. figure 35 shows a typical waveform in dcm with a 1 a load current. between t 1 and t 2 the inductor current ramps down. the current flows through the source drain of the low-side fet and creates a voltage drop across the fet with a slightly negative switch node. as the inductor current ramps down to 0 a, the switch voltage approaches 0 v, as seen just before t 2 . when the switch voltage is approximately ?6 mv, the low-side fet is turned off. figure 34 shows a small, dampened ringing at t 2 . this is caused by the lc created from capacitance on the switch node, including the c ds of the fets and the output inductor. this ringing is normal. the adp3208 automatically goes into dcm with a light load. figure 35 shows the typical dcm waveform of the adp3208. as the load increases, the adp 3208 enters into ccm. in dcm, frequency decreases with load current. figure 36 shows switching frequency vs. load current for a typical design. in dcm, switching frequency is a function of the inductor, load current, input voltage, and output voltage. switch node l drvl drvh q1 q2 c output voltage load input v oltage 06374-031 figure 30. buck topology l c on off load 06374-032 figure 31. buck topology inductor current during t 0 and t 1 l c on off load 06374-033 figure 32. buck topology inductor current during t 1 and t 2 l c off off load 06374-034 figure 33. buck topology inductor current during t 2 and t 3 inductor current switch node voltage t 0 t 1 t 2 t 3 t 4 06374-035 figure 34. inductor current and switch node in dcm 06374-036 3 1 2 4 2 s/div switch node 5v/div low-side gate drive 5v/div output voltage 20mv/div inductor current 5a/div figure 35. single-phase waveforms in dcm with 1 a load current 400 0 014 06374-037 load current (a) frequency (khz) 350 300 250 200 150 100 50 24681012 19v input 9v input figure 36. single-phase ccm/dcm frequency vs. load current
ADP3208A rev. 2 | page 23 of 38 | www.onsemi.com output crowbar to prevent the cpu and other external components from damage due to overvoltage, the adp3208 turns off the drvh1 and drvh2 outputs and turns on the drvl1 and drvl2 outputs when the output voltage exceeds the ovp threshold (1.7 v typical). turning on the low-side mosfets forces the output capacitor to discharge and the current to reverse, due to current build up in the inductors. if the output overvoltage is due to a drain-source short of the high-side mosfet, turning on the low-side mosfet results in a crowbar across the input voltage rail. the crowbar action blows the fuse of the input rail, breaking the circuit and thus protecting the microprocessor from destruction. when the ovp feature is triggered, the adp3208 is latched off. the latch-off function can be reset by removing and reapplying vcc to the adp3208 or by briefly pulling the en pin low. pulling ttsns to less than 1 v disables the overvoltage protection function. in this configuration, vrtt should be tied to ground. reverse voltage protection very large reverse current in inductors can cause negative vcore voltage, which is harmful to the cpu and other output components. the adp3208 provides a reverse voltage protection (rvp) function without additional system cost. the vcore voltage is monitored through the csref pin. when the csref pin voltage drops to less than ?300 mv, the adp3208 triggers the rvp function by disabling all pwm outputs and driving drvl1 and drvl2 low, thus turning off all mosfets. the reverse inductor currents can be quickly reset to 0 by discharging the built-up energy in the inductor into the input dc voltage source via the forward-biased body diode of the high-side mosfets. the rvp function is terminated when the csref pin voltage returns to greater than ?100 mv. sometimes the crowbar feature inadvertently causes output reverse voltage because turning on the low-side mosfets results in a very large reverse inductor current. to prevent damage to the cpu caused from negative voltage, the adp3208 maintains its rvp monitoring function even after ovp latch off. during ovp latch off, if the csref pin voltage drops to less than ?300 mv, the low-side mosfets is turned off. drvl outputs are allowed to turn back on when the csref voltage recovers to greater than ?100 mv. output enable and uvlo for the adp3208 to begin switching, the vcc supply voltage to the controller must be greater than the vccok threshold and the en pin must be driven high. if the vcc voltage is less than the vccuvlo threshold or the en pin is a logic low, the adp3208 shuts off. in shutdown mode, the controller holds the pwm outputs low, shorts the capacitors of the ss and pgdelay pins to ground, and drives the drvh and drvl outputs low. the user must adhere to proper power-supply sequencing during start-up and shutdown of the adp3208. all input pins must be at ground prior to removing or applying vcc, and all output pins should be left in high impedance state while vcc is off. thermal throttling control the adp3208 includes a thermal monitoring circuit to detect whether the temperature of the vr has exceeded a user-defined thermal throttling threshold. the thermal monitoring circuit requires an external resistor divider connected between the vcc pin and gnd. the divider consists of an ntc thermistor and a resistor. to generate a voltage that is proportional to temperature, the midpoint of the divider is connected to the ttsns pin. an internal comparator circuit compares the ttsns voltage to half the vcc threshold and outputs a logic level signal at the vrtt output when the temperature trips the user-set alarm threshold. the vrtt output is designed to drive an external transistor that in turn provides the high current, open-drain vrtt signal required by the imvp-6+ specification. the internal vrtt comparator has a hysteresis of approximately 100 mv to prevent high frequency oscillation of vrtt when the temperature approaches the set alarm point.
ADP3208A rev. 2 | page 24 of 38 | www.onsemi.com power monitor function the adp3208 includes a power monitor. the circuit creates the product of the output voltage and the output current. the multiplication is done by converting the differential current sense signal from cscomp to csref into a pulse-modulated periodic signal stream and then scaling that signal with the output voltage. the duty cycle of the pulse-modulated pmon signal is proportional to the current, and the amplitude is proportional to the voltage. the maximum load current that corresponds to the full-scale (100%) modulated signal can be adjusted by a resistor, rpmonfs, tied from pmonfs to gnd. rpmonfs also affects the clock frequency of the pwm circuit. an rc low path filter connected to the pmon output demodulates the pwm pulse stream and creates averaged output current or power information, depending on which rail the open-drain pmon output is pulled up to. if pmon is pulled up to a dc voltage, the rc-filtered voltage is proportional to the averaged load current. figure 37 shows the pmon configuration used to monitor load current. pmon pmonfs adp3208 13 14 dc voltage current signal pmon pwm r pull up r filter c filter r pmonfs 06374-038 figure 37. pmon current monitor configuration if pmon is pulled up to the converter output node, the demodulated voltage becomes proportional to the averaged power (see figure 38). pmon pmonfs adp3208 13 14 v core power signal pmon pwm r pull up r filter c filter r pmonfs 06374-038 figure 38. pmon power monitor configuration
ADP3208A rev. 2 | page 25 of 38 | www.onsemi.com table 6. vid codes vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 0 0 0 0 0 0 0 1.5000 v 0 0 0 0 0 0 1 1.4875 v 0 0 0 0 0 1 0 1.4750 v 0 0 0 0 0 1 1 1.4625 v 0 0 0 0 1 0 0 1.4500 v 0 0 0 0 1 0 1 1.4375 v 0 0 0 0 1 1 0 1.4250 v 0 0 0 0 1 1 1 1.4125 v 0 0 0 1 0 0 0 1.4000 v 0 0 0 1 0 0 1 1.3875 v 0 0 0 1 0 1 0 1.3750 v 0 0 0 1 0 1 1 1.3625 v 0 0 0 1 1 0 0 1.3500 v 0 0 0 1 1 0 1 1.3375 v 0 0 0 1 1 1 0 1.3250 v 0 0 0 1 1 1 1 1.3125 v 0 0 1 0 0 0 0 1.3000 v 0 0 1 0 0 0 1 1.2875 v 0 0 1 0 0 1 0 1.2750 v 0 0 1 0 0 1 1 1.2625 v 0 0 1 0 1 0 0 1.2500 v 0 0 1 0 1 0 1 1.2375 v 0 0 1 0 1 1 0 1.2250 v 0 0 1 0 1 1 1 1.2125 v 0 0 1 1 0 0 0 1.2000 v 0 0 1 1 0 0 1 1.1875 v 0 0 1 1 0 1 0 1.1750 v 0 0 1 1 0 1 1 1.1625 v 0 0 1 1 1 0 0 1.1500 v 0 0 1 1 1 0 1 1.1375 v 0 0 1 1 1 1 0 1.1250 v 0 0 1 1 1 1 1 1.1125 v 0 1 0 0 0 0 0 1.1000 v 0 1 0 0 0 0 1 1.0875 v 0 1 0 0 0 1 0 1.0750 v 0 1 0 0 0 1 1 1.0625 v 0 1 0 0 1 0 0 1.0500 v 0 1 0 0 1 0 1 1.0375 v 0 1 0 0 1 1 0 1.0250 v 0 1 0 0 1 1 1 1.0125 v 0 1 0 1 0 0 0 1.0000 v 0 1 0 1 0 0 1 0.9875 v 0 1 0 1 0 1 0 0.9750 v 0 1 0 1 0 1 1 0.9625 v 0 1 0 1 1 0 0 0.9500 v 0 1 0 1 1 0 1 0.9375 v 0 1 0 1 1 1 0 0.9250 v 0 1 0 1 1 1 1 0.9125 v 0 1 1 0 0 0 0 0.9000 v 0 1 1 0 0 0 1 0.8875 v 0 1 1 0 0 1 0 0.8750 v 0 1 1 0 0 1 1 0.8625 v 0 1 1 0 1 0 0 0.8500 v 0 1 1 0 1 0 1 0.8375 v 0 1 1 0 1 1 0 0.8250 v 0 1 1 0 1 1 1 0.8125 v 0 1 1 1 0 0 0 0.8000 v 0 1 1 1 0 0 1 0.7875 v 0 1 1 1 0 1 0 0.7750 v 0 1 1 1 0 1 1 0.7625 v 0 1 1 1 1 0 0 0.7500 v vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 0 1 1 1 1 0 1 0.7375 v 0 1 1 1 1 1 0 0.7250 v 0 1 1 1 1 1 1 0.7125 v 1 0 0 0 0 0 0 0.7000 v 1 0 0 0 0 0 1 0.6875 v 1 0 0 0 0 1 0 0.6750 v 1 0 0 0 0 1 1 0.6625 v 1 0 0 0 1 0 0 0.6500 v 1 0 0 0 1 0 1 0.6375 v 1 0 0 0 1 1 0 0.6250 v 1 0 0 0 1 1 1 0.6125 v 1 0 0 1 0 0 0 0.6000 v 1 0 0 1 0 0 1 0.5875 v 1 0 0 1 0 1 0 0.5750 v 1 0 0 1 0 1 1 0.5625 v 1 0 0 1 1 0 0 0.5500 v 1 0 0 1 1 0 1 0.5375 v 1 0 0 1 1 1 0 0.5250 v 1 0 0 1 1 1 1 0.5125 v 1 0 1 0 0 0 0 0.5000 v 1 0 1 0 0 0 1 0.4875 v 1 0 1 0 0 1 0 0.4750 v 1 0 1 0 0 1 1 0.4625 v 1 0 1 0 1 0 0 0.4500 v 1 0 1 0 1 0 1 0.4375 v 1 0 1 0 1 1 0 0.4250 v 1 0 1 0 1 1 1 0.4125 v 1 0 1 1 0 0 0 0.4000 v 1 0 1 1 0 0 1 0.3875 v 1 0 1 1 0 1 0 0.3750 v 1 0 1 1 0 1 1 0.3625 v 1 0 1 1 1 0 0 0.3500 v 1 0 1 1 1 0 1 0.3375 v 1 0 1 1 1 1 0 0.3250 v 1 0 1 1 1 1 1 0.3125 v 1 1 0 0 0 0 0 0.3000 v 1 1 0 0 0 0 1 0.2875 v 1 1 0 0 0 1 0 0.2750 v 1 1 0 0 0 1 1 0.2625 v 1 1 0 0 1 0 0 0.2500 v 1 1 0 0 1 0 1 0.2375 v 1 1 0 0 1 1 0 0.2250 v 1 1 0 0 1 1 1 0.2125 v 1 1 0 1 0 0 0 0.2000 v 1 1 0 1 0 0 1 0.1875 v 1 1 0 1 0 1 0 0.1750 v 1 1 0 1 0 1 1 0.1625 v 1 1 0 1 1 0 0 0.1500 v 1 1 0 1 1 0 1 0.1375 v 1 1 0 1 1 1 0 0.1250 v 1 1 0 1 1 1 1 0.1125 v 1 1 1 0 0 0 0 0.1000 v 1 1 1 0 0 0 1 0.0875 v 1 1 1 0 0 1 0 0.0750 v 1 1 1 0 0 1 1 0.0625 v 1 1 1 0 1 0 0 0.0500 v 1 1 1 0 1 0 1 0.0375 v 1 1 1 0 1 1 0 0.0250 v 1 1 1 0 1 1 1 0.0125 v 1 1 1 1 0 0 0 0.0000 v 1 1 1 1 0 0 1 0.0000 v
ADP3208A rev. 2 | page 26 of 38 | www.onsemi.com vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 1 1 1 1 0 1 0 0.0000 v 1 1 1 1 0 1 1 0.0000 v 1 1 1 1 1 0 0 0.0000 v vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 1 1 1 1 1 0 1 0.0000 v 1 1 1 1 1 1 0 0.0000 v 1 1 1 1 1 1 1 0.0000 v en pwrgd clken fbrtn fb comp ss st bst1 drvh1 sw1 pvcc1 drvl1 pgnd1 pgnd2 pvcc2 p m o n p m o n f s c l i m c s c o m p c s r e f c s s u m r a m p v r p m 48 d p r s l p d p r s t p p s i v i d 0 v i d 1 v i d 2 v i d 3 v i d 4 adp3208 varfreq vrtt ttsns r p m r t g n d l l i n e v i d 5 v i d 6 s p sw2 drvh2 bst2 v c c 1 pgdelay drvl2 vid6 vid5 vid4 vid3 vid2 vid1 vid0 v ss d4, bat54c sot-23 c16 0.1 f r32 0 ? c15 4.7 f /15v x5r q4 irf7832 q2 irf7821 q3 irf7821 q5 irf7832 c101 1nf c17 10 f/25v x5r c18 10 f/25v x5r c19 10 f/25v x5r c20 10 f/25v x5r vdc r55 dnp c28 dnp d5 mbrs130lt3 psi dprstp dprslpvr r29 200k ? 1% r14 127k ? 1% v cor e vr on v ss thermistor r4, r6 should be placed close to the hot spot of each phase. ttsns r4 100k ? thermistor, 5% r6 100k ? thermistor, 5% v3.3s imvp6_pwrgd clken j22 pwrgd j23 r45 3k ? r46 3k ? c4, 2.7nf r12, 1.65k ? 1% c6, 330pf r13, 33.2k ? 1% c7, 220pf c8, 18pf ttsns q17 2n7002 v5s v core r25, 115k ? , 1% r16 237k ? 1% r24, 115k ? , 1% r51, dnp r52, dnp j7 con2 csref vdc c27 10nf j1 pmon r28 3k ? r27 49.9k ? , 1% r20 dnp r19 0 ? c30 dnp r57 0 ? c14 1nf r18 0 ? r17 280k ? 1% c11 1nf r15 221k ? 1% c81 1nf r23 220k ? thermistor, 5% place r23 close to output inductor of phase 1 r22 73.2k ? 1% r21 165k ? , 1% c12 dnp c13 1.5nf x7r, 10% c47 10 f/6.3v x5r c48 10 f/6.3v x5r c45 10 f/6.3v x5r c46 10 f/6.3v x5r c43 10 f/6.3v x5r c44 10 f/6.3v x5r c41 10 f/6.3v x5r c42 10 f/6.3v x5r c39 10 f/6.3v x5r c40 10 f/6.3v x5r c49 10 f/6.3v x5r c50 10 f/6.3v x5r c37 10 f/6.3v x5r c38 10 f/6.3v x5r c35 10 f/6.3v x5r c36 10 f/6.3v x5r c51 10 f/6.3v x5r c52 10 f/6.3v x5r c33 10 f/6.3v x5r c34 10 f/6.3v x5r c53 10 f/6.3v x5r c54 10 f/6.3v x5r c55 10 f/6.3v x5r c56 10 f/6.3v x5r c57 10 f/6.3v x5r c58 10 f/6.3v x5r c59 10 f/6.3v x5r c60 10 f/6.3v x5r c61 10 f/6.3v x5r c62 10 f/6.3v x5r c63 10 f/6.3v x5r c64 10 f/6.3v x5r vccsense vsssense r10 100 ? r50 100 ? j5 vcc_s j6 vss_s vcc(core) vcc(core) rtn jp1 shortpin four pieces panasonic sp cap (sd) or sanyo poscap v ss d7, bat54c, sot-23 c22 0.1 f r33 0 ? c21 4.7 f /15v x5r q9 irf7832 q7 irf7821 q8 irf7821 q10 irf7832 c102 1nf c23 10 f/25v x5r c24 10 f/25v x5r c24 10 f/25v x5r c26 10 f/25v x5r vdc r56 dnp c29 dnp d8 mbrs130lt3 r34 dnp r42 0 ? l1 panasonic(etqp5lr33xfc) 0.33 h/esr = 0.8m ? l2 0.33 h/esr = 0.8m ? j8 sw1 j9 sw2 r53 0 ? r54 0 ? r31 dnp r30 dnp rs1 (optional) rs2 (optional) csref r1, 7.32k ? 1% r3 7.32k ? 1% d3, bat54c, sot-23 d1, bat54c sot-23 r7 1m ? c1, 10nf x7r c2 1 f/16v x7r r8, 10 ? ce13 33 f/10v c3 1 f/16v x7r r2 dnp r5 100k ? c9 12nf c10, 680pf nop 5% r9, dnp r26, 100k ? j2 ss j4 st j3 comp r11, 0 ? 2 1 c5 1nf c65 dnp c66 dnp c67 330 f c68 330 f c69 330 f c70 330 f 06374-040 vrtt figure 39. typical dual-phase application circuit
ADP3208A rev. 2 | page 27 of 38 | www.onsemi.com application information the design parameters for a typical imvp-6+-compliant cpu core vr application are as follows: ? maximum input voltage (v inmax ) = 19 v ? minimum input voltage (v inmin ) = 8 v ? output voltage by vid setting (v vid ) = 1.4375 v ? maximum output current (i o ) = 40 a ? droop resistance (r o ) = 2.1 m ? nominal output voltage at 40 a load (v ofl ) = 1.3535 v ? static output voltage drop from no load to full load (v = v onl ? v ofl = 1.4375 v ? 1.3535 v = 84 mv ? maximum output current step (i o ) = 27.9 a ? number of phases (n) = 2 ? switching frequency per phase (f sw ) = 300 khz ? duty cycle at maximum input voltage (d max ) = 0.18 v ? duty cycle at minimum input voltage (d min ) = 0.076 v setting the clock frequency for pwm in pwm operation, the adp3208 uses a fixed-frequency control architecture. the frequency is set by an external timing resistor (rt). the clock frequency and the number of phases determine the switching frequency per phase, which relates directly to the switching losses and the sizes of the inductors and input and output capacitors. for a dual-phase design, a clock frequency of 600 khz sets the switching frequency to 300 khz per phase. this selection represents the trade-off between the switching losses and the minimum sizes of the output filter components. to achieve a 600 khz oscillator frequency at a vid voltage of 1.5 v, rt must be 250 k. alternatively, the value for rt can be calculated by using the following equation: k 35 pf 2 . 7 2 v 0 . 1 ? + = sw vid f n v rt (1) where: 7.2 pf and 35 k are internal ic component values. v vid is the vid voltage in volts. n is the number of phases. f sw is the switching frequency in hertz for each phase. for good initial accuracy and frequency stability, it is recommended to use a 1% resistor. setting the switching frequency for rpm operation of phase 1 during the rpm operation of phase 1, the adp3208 runs in pseudoconstant frequency if the load current is high enough for continuous current mode. while in dcm, the switching frequency is reduced with the load current in a linear manner. to save power with light loads, lower switching frequency is usually preferred during rpm operation. however, the v core ripple specification of imvp-6+ sets a limitation for the lowest switching frequency. therefore, depending on the inductor and output capacitors, the switching frequency in rpm can be equal to, greater than, or less than its counterpart in pwm. a resistor between the vrpm and rpm pins sets the pseudo- constant frequency as follows: sw r r vid r vid rpm f c r v d a v rt r ? + = ) 1 ( ) v 0 . 1 ( 4 (2) where: a r is the internal ramp amplifier gain. c r is the internal ramp capacitor value. r r is an external resistor on the ramp pin to set the internal ramp magnitude (see the ramp resistor selection section for information about the design of r r resistance). if r r = 280 k, the following resistance results in 300 khz switching frequency in rpm operation. k 246 khz 300 pf 5 k 280 4375 . 1 ) 076 . 0 1 ( 2 . 0 v 0 . 1 v 4375 . 1 k 237 4 = ? + = rpm r soft start and current limit latch-off delay times the soft start and current limit latch-off delay functions share the ss pin; consequently, these parameters must be considered together. first, set c ss for the soft start ramp. this ramp is generated with an 8 a internal current source. the value for c ss can be calculated as boot ss ss v t c = a 8 (3) where: v boot is the boot voltage for the cpu and is defined in imvp-6+ as 1.2 v. t ss is the desired soft start time and is recommended in imvp-6+ to be less than 3 ms. therefore, assuming a desired soft start time of 2 ms, c ss is 13.3 nf, and the closest standard capacitance is 12 nf. after c ss is set, the current limit latch-off time can be calculated by using the following equation: a 2 v 2 . 1 ss delay c t = (4) where c ss is 7.2 ms.
ADP3208A rev. 2 | page 28 of 38 | www.onsemi.com pwrgd delay timer the pwrgd delay, t cpu_pwrgd , is defined in imvp-6+ as the period between the clken assertion and the pwrgd assertion. it is programmed by a capacitor connected to the pgdelay pin and calculated as follows: v 9 . 2 a 2 _ pwrgd cpu pgdelay t c = (5) imvp-6+ specifies that the pwrgd delay is between 3 ms and 20 ms. assuming a 5 ms pwrgd delay, c pgdelay is 4.7 nf. inductor selection the choice of inductance determines the ripple current of the inductor. less inductance results in more ripple current, which increases the output ripple voltage and the conduction losses in the mosfets. however, this allows the use of smaller-size inductors, and for a specified peak-to-peak transient deviation, it allows less total output capacitance. conversely, a higher inductance means lower ripple current and reduced conduction losses, but it requires larger-size inductors and more output capacitance for the same peak-to-peak transient deviation. for a multiphase converter, the practical value for peak-to-peak inductor ripple current is less than 50% of the maximum dc current of that inductor. equation 6 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current. equation 7 can be used to determine the minimum inductance based on a given output ripple voltage. l f d v i sw min vid r ? = ) 1 ( (6) ripple sw min min o vid v f d d n r v l ? ? ) 1 ( )) ( 1 ( (7) solving equation 7 for a 16 mv peak-to-peak output ripple voltage yields () nh 493 mv 16 khz 0 0 3 ) 076 . 0 1 ( 076 . 0 2 1 m 1 . 2 v 75 3 4 1. = ? ? l if the resultant ripple voltage is less than the initially selected value, the inductor can be changed to a smaller value until the ripple value is met. this iter ation allows optimal transient response and minimum output decoupling. the smallest possible inductor sh ould be used to minimize the number of output capacitors. choosing a 490 nh inductor is a good choice for a starting point, and it provides a calculated ripple current of 9.0 a. the inductor should not saturate at the peak current of 24.5 a, and it should be able to handle the sum of the power dissipation caused by the windings average current (20 a) plus the ac core loss. in this example, 330 nh is used. another important factor in the inductor design is the dcr, which is used for measuring the phase currents. too large of a dcr causes excessive power losses, whereas too small of a value leads to increased measurement error. for this example, an inductor with a dcr of 0.8 m is used. selecting a stan dard inductor after the inductance and dcr are known, select a standard inductor that best meets the over all design goals. it is also important to specify the inductance and dcr tolerance to maintain the accuracy of the system. using 20% tolerance for the inductance and 15% for the dcr at room temperature are reasonable values that most manufacturers can meet. power inductor manufacturers the following companies provide surface-mount power inductors optimized for high power applications upon request. ? vishay dale electronics, inc. (605) 665-9301 ? panasonic (714) 373-7334 ? sumida electric company (847) 545-6700 ? nec tokin corporation (510) 324-4110 output droop resistance the design requires that the regulator output voltage measured at the cpu pins decreases when the output current increases. the specified voltage drop corresponds to the droop resistance (r o ). the output current is measured by summing the currents of the resistors monitoring the voltage across each inductor and by passing the signal through a low-pass filter. the summing is implemented by the cs amplifier that is configured with resistor r ph(x) (summer) and resistors r cs and c cs (filters). the output resistance of the regulator is set by the following equations: sense x ph cs o r r r r = ) ( (8) cs sense cs r r l c = (9) where r sense is the dcr of the output inductors. either r cs or r ph(x) can be chosen for added flexibility. due to the current drive ability of the cscomp pin, the r cs resistance should be greater than 100 k. for example, initially select r cs to be equal to 200 k, and then use equation 9 to solve for c cs : nf 1 . 2 k 200 m 8 . 0 nh 330 = = cs c if c cs is not a standard capacitance, r cs can be tuned. for example, if the optimal c cs capacitance is 1.5 nf, adjust r cs to 280 k. for best accuracy, c cs should be a 5% npo capacitor. in this example, a 220 k is used for r cs to achieve optimal results.
ADP3208A rev. 2 | page 29 of 38 | www.onsemi.com next, solve for r ph(x) by rearranging equation 8 as follows: k 8 . 83 k 220 m 1 . 2 m 8 . 0 ) ( = x ph r the standard 1% resistor for r ph(x) is 86.6 k. inductor dcr temperature correction if the dcr of the inductor is used as a sense element and copper wire is the source of the dcr, the temperature changes associated with the inductors winding must be compensated for. fortunately, copper has a well-known temperature coefficient (tc) of 0.39%/c. if r cs is designed to have an opposite but equal percentage of change in resistance, it cancels the temperature variation of the inductors dcr. due to the nonlinear nature of ntc thermistors, series resistors r cs1 and r cs2 (see figure 40) are needed to linearize the ntc and produce the desired temperature coefficient tracking. c cs1 c cs2 cscomp cssum csref r cs1 r cs2 adp3208 to switch nodes r ph1 place as close as possible to nearest inductor or low-side mosfet 17 19 18 keep this path as short as possible and away from switch node lines r ph2 to v core sense r th 06374-041 figure 40. temperature-compensation circuit values the following procedure and expressions yield values for r cs1 , r cs2 , and r th (the thermistor value at 25c) for a given r cs value. 1. select an ntc to be used based on its type and value. because the value needed is not yet determined, start with a thermistor with a value close to r cs and an ntc with an initial tolerance of better than 5%. 2. find the relative resistance value of the ntc at two temperatures. the appropriate temperatures will depend on the type of ntc, but 50c and 90c have been shown to work well for most types of ntcs. the resistance values are called a (a is r th (50c)/r th (25c)) and b (b is r th (90c)/r th (25c)). note that the relative value of the ntc is always 1 at 25c. 3. find the relative value of r cs required for each of the two temperatures. the relative value of r cs is based on the percentage of change needed, which is initially assumed to be 0.39%/c in this example. the relative values are called r 1 (r 1 is 1/(1+ tc ( t 1 ? 25))) and r 2 (r 2 is 1/(1 + tc ( t 2 ? 25))), where tc is 0.0039, t 1 is 50c, and t 2 is 90c. 4. compute the relative values for r cs1 , r cs2 , and r th by using the following equations: ) ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) ( 2 1 1 2 2 1 2 b a r a b r b a r a b r b a r r b a r cs ? ? ? ? ? ? + ? ? ? = (10) 2 1 2 1 1 1 ) 1 ( cs cs cs r r a r a r ? ? ? ? = 1 2 1 1 1 1 cs cs th r r r ? ? = 5. calculate r th = r th r cs , and then select a thermistor of the closest value available. in addition, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: ) ( ) ( calculated th actual th r r k = (11) 6. calculate values for r cs1 and r cs2 by using the following equations: 1 1 cs cs cs r k r r = (12) )) ( ) 1 (( 2 2 cs cs cs r k k r r + ? = for example, if a thermistor value of 100 k is selected in step 1, an available 0603-size thermist or with a value close to r cs is the vishay nths0603n04 ntc thermistor, which has resistance values of a = 0.3359 and b = 0.0771. using the equations in step 4, r cs1 is 0.359, r cs2 is 0.729, and r th is 1.094. solving for r th yields 241 k, so a thermistor of 220 k would be a reasonable selection, making k equal to 0.913. finally, r cs1 and r cs2 are found to be 72.1 k and 166 k. choosing the closest 1% resistor for r cs2 yields 165 k. to correct for this approximation, 73.3 k is used for r cs1 .
ADP3208A rev. 2 | page 30 of 38 | www.onsemi.com c out selection the required output decoupling for processors and platforms is typically recommended by intel. for systems containing both bulk and ceramic capacitors, however, the following guidelines can be a helpful supplement. select the number of ceramics and determine the total ceramic capacitance (c z ). this is based on the number and type of capacitors used. keep in mind that the best location to place ceramic capacitors is inside the socket; however, the physical limit is 20 0805-size pieces in side the socket. additional ceramic capacitors can be placed along the outer edge of the socket. a combined ceramic capacitor value of 200 f to 300 f is recommended and is usually composed of multiple 10 f or 22 f capacitors. ensure that the total amount of bulk capacitance (c x ) is within its limits. the upper limit is dependent on the vid on-the-fly output voltage stepping (voltage step v v in time t v with error of v err ); the lower limit is based on meeting the critical capacitance for load release at a given maximum load step, i o . the current version of the imvp-6+ specification allows a maximum v core overshoot (v osmax ) of 10 mv more than the vid voltage for a step-off load current. () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + z vid o osmax o o min x c v i v r n i l c (13) z o v vid v vid v 2 o 2 max x c l r k n v v t v v r k n l c ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 1 1 2 ) ( where ? ? ? ? ? ? ? ? ? = v err v v k ln (14) to meet the conditions of these expressions and the transient response, the esr of the bulk capacitor bank (r x ) should be less than two times the droop resistance, r o . if the c x(min) is greater than c x(max) , the system does not meet the vid on-the-fly and/or the deeper sleep exit specifications and may require less inductance or more phases. in addition, the switching frequency may have to be increased to maintain the output ripple. for example, if 30 pieces of 10 f, 0805-size mlc capacitors (c z = 300 f) are used, the fastest vid voltage change is when the device exits deeper sleep, during which the v core change is 220 mv in 22 s with a setting error of 10 mv. if k = 3.1, solving for the bulk capacitance yields () mf 0 . 1 f 300 v 4375 . 1 a 9 . 27 mv 10 m 1 . 2 2 a 9 . 27 nh 330 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + min x c () v 4375 . 1 ) m 1 . 2 ( 1 . 3 2 mv 220 nh 330 2 2 max x c f 300 1 nh 0 49 mv 0 22 m 1 . 2 1 . 3 2 v 75 3 4 1. s 2 2 1 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 21 mf using six 330 f panasonic sp capacitors with a typical esr of 7 m each yields c x = 1.98 mf and r x = 1.2 m. ensure that the esl of the bulk capacitors (l x ) is low enough to limit the high frequency ringing during a load change. this is tested using 2 2 o z x q r c l (15) () nh 2 2 m 1 . 2 f 300 2 = x l where: q is limited to the square root of 2 to ensure a critically damped system. l x is about 150 ph for the six sp capacitors, which is low enough to avoid ringing during a load change. if the l x of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased to prevent excessive ringing. for this multimode control technique, an all ceramic capacitor design can be used if the conditions of equations 13, 14, and 15 are satisfied.
ADP3208A rev. 2 | page 31 of 38 | www.onsemi.com power mosfets for typical 20 a per phase applications, the n-channel power mosfets are selected for two high-side switches and two or three low-side switches per phase. the main selection parameters for the power mosfets are v gs(th) , q g , c iss , c rss , and r ds(on) . because the voltage of the gate driver is 5 v, logic- level threshold mosfets must be used. the maximum output current, i o , determines the r ds(on) requirement for the low-side (synchronous) mosfets. in the adp3208, currents are balanced between phases; the current in each low-side mosfet is the output current divided by the total number of mosfets (n sf ). with conduction losses being dominant, the following expression shows the total power that is dissipated in each synchronous mosfet in terms of the ripple current per phase (i r ) and the average total output current (i o ): ) ( 2 2 12 1 ) 1 ( sf ds sf r sf o sf r n i n n i d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? = (16) where: d is the duty cycle and is approximately the output voltage divided by the input voltage. i r is the inductor peak-to-peak ripple current and is approximately sw out r f l v d i ? = ) 1 ( knowing the maximum output current and the maximum allowed power dissipation, the user can calculate the required r ds(on) for the mosfet. for 8-lead soic or 8-lead soic- compatible mosfets, the junction-to-ambient (pcb) thermal impedance is 50c/w. in the worst case, the pcb temperature is 70c to 80c during heavy load operation of the notebook, and a safe limit for p sf is 0.8 w~1.0 w at 120c junction temperature. therefore, for this example (40 a maximum), the r ds(sf) per mosfet is less than 8.5 m for two pieces of low-side mosfets. this r ds(sf) is also at a junction temperature of about 120c; therefore, the r ds(sf) per mosfet should be less than 6 m at room temperature, or 8.5 m at high temperature. another important factor for the synchronous mosfet is the input capacitance and feedback capacitance. the ratio of the feedback to input must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous mosfets when the switch node goes high. the high-side (main) mosfet must be able to handle two main power dissipation components: conduction losses and switching losses. switching loss is related to the time for the main mosfet to turn on and off and to the current and voltage that are being switched. basing the switching speed on the rise and fall times of the gate driver impedance and mosfet input capacitance, the following expression provides an approximate value for the switching loss per main mosfet: iss mf g mf o dc sw mf s c n n r n i v f p = 2 ) ( (17) where: n mf is the total number of main mosfets. r g is the total gate resistance. c iss is the input capacitance of the main mosfet. the most effective way to reduce switching loss is to use lower gate capacitance devices. the conduction loss of the main mosfet is given by the following equation: ) ( 2 2 ) ( 12 1 mf ds mf r mf o mf c r n i n n i d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = (18) where r ds(mf) is the on resistance of the mosfet. typically, a user wants the highest speed (low c iss ) device for a main mosfet, but such a device usually has higher on resistance. therefore, the user must select a device that meets the total power dissipation (0.8 w~1.0 w for an 8-lead soic) when combining the switching and conduction losses. for example, an irf7821 device co uld be selected as the main mosfet (four in total; that is, n mf = 4), with approximately c iss = 1010 pf (maximum) and r ds(mf) = 18 m (maximum at tj = 120c), and an ir7832 device could be selected as the synchronous mosfet (four in total; that is, n sf = 4), with r ds(sf) = 6.7 m (maximum at tj = 120c). solving for the power dissipation per mosfet at i o = 40 a and i r = 9.0 a yields 630 mw for each synchronous mosfet and 590 mw for each main mosfet. a third synchronous mosfet is an option to further increase the conversion efficiency and reduce thermal stress. finally, consider the power dissipation in the driver for each phase. this is best described in terms of the q g for the mosfets and is given by the following equation: () vcc i q n q n n f p cc gsf sf gmf mf sw drv ? ? ? ? ? ? + + = 2 (19) where q gmf is the total gate charge for each main mosfet, and q gsf is the total gate charge for each synchronous mosfet. the previous equation also shows the standby dissipation (i cc times the vcc) of the driver.
ADP3208A rev. 2 | page 32 of 38 | www.onsemi.com ramp resistor selection the ramp resistor (r r ) is used to set the size of the internal pwm ramp. the value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. use the following expression to determine a starting value: r ds d r r c r a l a r = 3 (20) k 256 pf 5 m 4 . 3 5 3 nh 330 2 . 0 = = r r where: a r is the internal ramp amplifier gain. a d is the current balancing amplifier gain. r ds is the total low-side mosfet on resistance. c r is the internal ramp capacitor value. another consideration in the selection of r r is the size of the internal ramp voltage (see equation 21). for stability and noise immunity, keep the ramp size larger than 0.5 v. taking this into consideration, the value of r r in this example is selected as 280 k. the internal ramp voltage magnitude can be calculated as follows: sw r r vid r r f c r v d a v ? = ) 1 ( (21) v 59 . 0 khz 300 pf 5 k 280 v 3475 . 1 ) 076 . 0 1 ( 2 . 0 = ? = r v the size of the internal ramp can be increased or decreased. if it is increased, stability and transient response improves but thermal balance degrades. conversely, if the ramp size is decreased, thermal balance improves but stability and transient response degrade. in the denominator of equation 20, the factor of 3 sets the minimum ramp size that produces an optimal combination of good stability, transient response, and thermal balance. comp pin ramp in addition to the internal ramp , there is a ramp signal on the comp pin due to the droop voltage and output voltage ramps. this ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the pwm input: () ? ? ? ? ? ? ? ? ? ? = o x sw r rt r c f n d n v v 1 2 1 (22) where c x is the total bulk capacitance, and r o is the droop resistance of the regulator. for this example, the overall ramp signal is 1.85 v. current limit setpoint to select the current limit setpoint, the resistor value for r clim must be determined. the current limi t threshold for the adp3208 is set with r clim . r clim can be found using the following equation: n r i r r r ph clim sense cs clim = a 10 2 10 (23) where: r ph is the resistor connecting the current sense resistor or inductor switch node to the current sense amplifier. r cs is the current sense amplifier feedback resistor. r sense is the sense current resistor or the inductor dcr. n is the number of phases. i clim is the current limit setpoint. if r clim is greater than 500 k, the current limit may be lower than expected and require an adjustment of r clim . in this example, i clim is the average current limit for the output of the supply. for this example, choosing 60 a for i clim , results in an r clim of 126 k, and the closest 1% standard resistance is 127 k. the following equation determines the per phase current limit previously described: 2 ) ( ) ( r max ds d bias r max comp phlim i r a v v v i ? ? ? = (24) where: v comp(max) is the maximum comp voltage and is 3.3 v. v bias is the comp pin bias voltage and is 1.0 v. a d is the current-balancing amplifier gain and is 5. using a v r of 0.59 v and a r ds(max) of 3.8 m (low-side on resistance at 150c) results in a per phase limit of 83 a. although this number may seem high, this current level can be achieved using only an absolute short at the output, and the current limit latch-off function shuts down the regulator before overheating can occur. this limit can be adjusted by changing the ramp voltage, v r . however, the per phase limit must be set to be greater than the average per phase current (i clim /n). there is also a per phase initial duty cycle limit at the maximum input voltage: r bias max comp min lim v v v d d ? = ) ( (25) for this example, the duty cycle limit at the maximum input voltage is 0.3 v when d is 0.076.
ADP3208A rev. 2 | page 33 of 38 | www.onsemi.com power monitor the pmon duty cycle is proportional to load current. r pmonfs sets the maximum duty cycle at the maximum current. a 10 1 ) 9 ( v r i r o load pmonfs + = (26) where i load is the load current in amps when pmon is 100% duty cycle, and r o is the droop resistance in ohms. when pmon is connected with a pull-up resistor to the output voltage, as shown in figure 38, the average pmon voltage is given by 1v - a) 10 ( 9 = monfs o load gfx r r i v pmon (27) feedback loop compensation design optimized compensation of the adp3208 allows the best possible response of the regulators output to a load change. the basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (r o ). with the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate, ensuring the optimal position and allowing the minimization of the output decoupling. with the multimode feedback structure of the adp3208, it is necessary to set the feedback compensation so that the converters output impedance works in parallel with the output decoupling. in addition, it is necessary to compensate for the several poles and zeros created by the output inductor and decoupling capacitors (output filter). a type iii compensator on the voltage feedback is adequate for proper compensation of the output filter. figure 41 shows the type iii amplifier used in the adp3208. figure 42 shows the locations of the two poles and two zeros created by this amplifier. r a adp3208 reference voltage output voltage c a c b c fb r fb comp fb 6 7 v oltage error amplifier 06374-042 figure 41. voltage error amplifier gain 0db frequency f p1 f z2 f p2 f z1 ?20db/dec ?20db/dec 06374-043 figure 42. poles and zeros of voltage error amplifier the following equations give the locations of the poles and zeros shown in figure 42. a a z r c f = 2 1 1 (28) fb fb z r c f = 2 1 2 (29) fb b a p r c c f + = ) ( 2 1 1 (30) a b a b a p c c r c c f + = 2 2 (31) the expressions that follow compute the time constants for the poles and zeros in the system and are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for pcb and component parasitic effects (see the tuning procedure for adp3208 section): + + + = vid rt l ds d o e v v r r a r n r (32) vid o x rt v r c n v d n l ? )) ( 1 ( 2 () x o o x o x a r r r r l r r c t ' ' ? + ? = (33) ( ) x o x b c r r r t ? + = ' (34) e vid sw ds d rt c r v f r a l v t ? ? ? ? ? ? ? ? ? = 2 (35) () o z o x o z x d r c r r c r c c t + ? = ' 2 (36) where: r' is the pcb resistance from the bulk capacitors to the ceramics and is approximately 0.4 m (assuming an 8-layer motherboard). r ds is the total low-side mosfet for on resistance per phase. a d is 5. v rt is 1.25 v. l x is 150 ph for the six panasonic sp capacitors.
ADP3208A rev. 2 | page 34 of 38 | www.onsemi.com the compensation values can be calculated as follows: b e a o a r r t r n c = (37) a c a c t r = (38) b b b r t c = (39) a d fb r t c = (40) the standard values for these components are subject to the tuning procedure described in the tuning procedure for adp3208 section. c in selection and input current di/dt reduction in continuous inductor-current mode, the source current of the high-side mosfet is approximately a square wave with a duty ratio equal to n v out / v in and an amplitude that is one-n th of the maximum output current. to prevent large voltage transients, use a low esr input capacitor sized for the maximum rms current. the maximum rms capacitor current occurs at the lowest input voltage and is given by 1 1 ? = d n i d i o crms (41) a 6 . 9 1 0.18 2 1 a 40 18 . 0 = ? = crms i where i o is the output current. in a typical notebook system, the battery rail decoupling is achieved by using mlc capacitors or a mixture of mlc capacitors and bulk capacitors. in this example, the input capacitor bank is formed by eight pieces of 10 f, 25 v mlc capacitors, with a ripple current rating of about 1.5 a each. soft transient setting as described in the theory of operation section, during the soft transient, the slew rate of the v core reference voltage change is controlled by the st pin capacitance. because the timing of exiting deeper sleep is critical, the st pin capacitance is set to satisfy the slew rate for a fast exit of deeper sleep as follows: c4e st slewrate c a 5 . 7 = (42) where: 7.5 a is the source/sink current of the st pin. slewrate c4e is the voltage slew rate for exiting deeper sleep and is defined as 10mv/a in the imvp-6+ specification. c st is 750 pf, and the closest standard capacitance is 680 pf. selecting thermal monitor components to monitor the temperature of a single-point hot spot, set r ttset1 equal to the ntc thermistors resistance at the alarm temperature. for example, if the alarm temperature for vrtt is 100c and a vishey thermist or (nths-0603n011003j) with a resistance of 100 k at 25c, or 6.8 k at 100c, is used, the user can set r ttset1 equal to 6.8 k (the r th1 at 100c). a dp3208 r ttset1 5v r th1 c tt r r 12 37 11 ttsns vcc vrtt 06374-044 figure 43. single-point thermal monitoring to monitor the temperature of multiple-point hot spots, use the configuration shown in figure 44. if any of the monitored hot spots reaches the alarm temperature, the vrtt signal is asserted. the following calculation sets the alarm temperature: mperature th1alarmte re f fd ref fd ttset1 r v v v v r ? + = 2 / 1 2 / 1 (43) where v fd is the forward drop voltage of the parallel diode. because the forward current is very small, the forward drop voltage is very low, that is, less than 100 mv. assuming the same conditions used for the single-point thermal monitoring examplethat is, an alarm temp erature of 100c and use of an nths-0603n011003j vishay thermistorsolving equation 42 gives a r ttset of 7.37 k, and the closest standard resistor is 7.32 k (1%). adp3208 r ttset1 5v r thn c tt r r 12 37 11 ttsns vcc vrtt r th2 r th1 r ttset2 r ttsetn 1m ? 06374-045 figure 44. multiple-point thermal monitoring the number of hot spots monitored is not limited. the alarm temperature of each hot spot can be individually set by using different values for r ttset1 , r ttset2 , r ttsetn .
ADP3208A rev. 2 | page 35 of 38 | www.onsemi.com tuning procedure for adp3208 set up and test the circuit 1. build a circuit based on the compensation values computed from the design spreadsheet. 2. connect a dc load to the circuit. 3. turn on the adp3208 and verify that it operates properly. 4. check for jitter with no lo ad and full load conditions. set the dc load line 1. measure the output voltage with no load (v nl ) and verify that this voltage is within the specified tolerance range. 2. measure the output voltage with a full load when the device is cold (v flcold ). allow the board to run for ~10 minutes with a full load and then measure the output when the device is hot (v flhot ). if the difference between the two measured voltages is more than a few millivolts, adjust r cs2 using equation 44. flhot nl flcold nl old cs new cs v v v v r r ? ? = ) ( 2 ) ( 2 (44) 3. repeat step 2 until no adjustment of r cs2 is needed. 4. compare the output voltage with no load to that with a full load using 5 a steps. compute the load line slope for each change and then find the average to determine the overall load line slope (r omeas ). 5. if the difference between r omeas and r o is more than 0.05 m, use the following equation to adjust the r ph values: o omeas old ph new ph r r r r = ) ( ) ( (45) 6. repeat steps 4 and 5 until no adjustment of r ph is needed. once this is achieved, do not change r ph , r cs1 , r cs2 , or r th for rest of procedure. 7. measure the output ripple with no load and with a full load with scope, making sure both are within the specifications. set the ac load line 1. remove the dc load from the circuit and connect a dynamic load. 2. connect the scope to the output voltage and set it to dc coupling mode with a time scale of 100 s/div. 3. set the dynamic load for a transient step of about 40 a at 1 khz with 50% duty cycle. 4. measure the output waveform (note that use of a dc offset on the scope may be necessary to see the waveform). try to use a vertical scale of 100 mv/div or finer. 5. the resulting waveform will be similar to that shown in figure 45. use the horizontal cursors to measure v acdrp and v dcdrp , as shown in figure 45. do not measure the under- shoot or overshoot that occurs immediately after the step. v dcdrp v acdrp 06374-046 figure 45. ac load line waveform 6. if the difference between v acdrp and v dcdrp is more than a couple of millivolts, use equation 44 to adjust c cs . it may be necessary to try several parallel values to obtain the right one because there are limited standard capacitor values available (it is a good idea to have locations for two capacitors in the layout for this reason). dcdrp acdrp old cs new cs v v c c = ) ( ) ( (46) 7. repeat steps 5 and 6 until no adjustment of c cs is needed. once this is achieved, do not change c cs for the rest of the procedure. 8. set the dynamic load step to its maximum step size (but do not use a step size that is larger than needed) and verify that the output waveform is square, meaning v acdrp and v dcdrp are equal. 9. ensure that the load step slew rate and the power-up slew rate are set to ~150 a/s to 250 a/s (for example, a load step of 50 a should take 200 ns to 300 ns) with no overshoot. some dynamic loads have an excessive overshoot at power-up if a minimum current is incorrectly set (this is an issue if a vtt tool is in use). set the initial transient 1. with the dynamic load set at its maximum step size, expand the scope time scale to 2 s/div to 5 s/div. this results in a waveform that may have two overshoots and one minor undershoot before achieving the final desired value after v droop (see figure 46).
ADP3208A rev. 2 | page 36 of 38 | www.onsemi.com v droop v tran2 v tran1 06374-047 figure 46. transient setting waveform, load step 2. if both overshoots are larger than desired, try the following adjustments in the order shown a. increase the resistance of the ramp resistor (r ramp ) by 25%. b. for v tran1 , increase c b or increase the switching frequency. c. for v tran2 , increase r a by 25% and decrease c a by 25%. if these adjustments do not change the response, it is because the system is limited by the output decoupling. check the output response and the switching nodes each time a change is made to ensure that the output decoupling is stable. 3. for load release (see figure 47), if v tranrel is larger than the imvp-6+ specified value, a greater percentage of output capacitance is needed. either increase the capacitance directly or decrease the inductor values. (if inductors are changed, however, it will be necessary to redesign the circuit using the spreadsheet and to repeat all tuning guide procedures). v droop v tranrel 06374-048 figure 47. transient setting waveform, load release layout and component placement the following guidelines are recommended for optimal performance of a switching regulator in a pc system. general recommendations 1. for best results, use a pcb of four or more layers. this should provide the needed versatility for control circuitry interconnections with optimal placement; power planes for ground, input, and output; and wide interconnection traces in the rest of the power delivery current paths. keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 m at room temperature. 2. when high currents must be routed between pcb layers, vias should be used liberall y to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 3. if critical signal lines (including the output voltage sense lines of the adp3208) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the signals at the expense of increasing signal ground noise. 4. an analog ground plane should be used around and under the adp3208 for referencing the components associated with the controller. this plane should be tied to the nearest ground of the output decoupling capacitor, but should not be tied to any other power circuitry to prevent power currents from flowing into the plane. 5. the components around the adp3208 should be located close to the controller with short traces. the most important traces to keep short and away from other traces are those to the fb and cssum pins. refer to figure 40 for more details on the layout for the cssum node. 6. the output capacitors should be connected as closely as possible to the load (or connector) that receives the power (for example, a microprocessor core). if the load is distributed, the capacitors should also be distributed and generally in proportion to where the load tends to be more dynamic. 7. avoid crossing signal lines over the switching power path loop, as described in the power circuitry section. power circuitry 1. the switching power path on the pcb should be routed to encompass the shortest possible length to minimize radiated switching noise energy (that is, emi) and conduction losses in the board. failure to take proper precautions often results in emi problems for the entire pc system as well as noise-relate d operational problems in the power-converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors and the power mosfets, including all interconnecting pcb traces and planes. the use of short, wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it
ADP3208A rev. 2 | page 37 of 38 | www.onsemi.com accommodates the high current demand with minimal voltage loss. 2. when a power-dissipating component (for example, a power mosfet) is soldered to a pcb, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the pcb, where a plane can more readily transfer heat to the surroundi ng air. to achieve optimal thermal dissipation, mirror the pad configurations used to heat sink the mosfets on the opposite side of the pcb. in addition, improvements in thermal performance can be obtained using the largest possible pad area. 3. the output power path should also be routed to encompass a short distance. the output power path is formed by the current path through the inductor, the output capacitors, and the load. 4. for best emi containment, a solid power ground plane should be used as one of the inner layers and extended under all power components. signal circuitry 1. the output voltage is sensed and regulated between the fb and fbrtn pins, and the traces of these pins should be connect to the signal ground of the load. to avoid differential mode noise pickup in the sensed signal, the loop area should be as small as possible. therefore, the fb and fbrtn traces should be routed adjacent to each other, atop the power ground plane, and back to the controller. 2. the feedback traces from the switch nodes should be connected as close as possible to the inductor. the csref signal should be kelvin connected to the center point of the copper bar, which is the v core common node for the inductors of all the phases. 3. on the back of the adp3208 package, there is a metal pad that can be used to heat sink the device. therefore, running vias under the adp3208 is not recommended because the metal pad may cause shorting between vias.
ADP3208A rev. 2 | page 38 of 38 | www.onsemi.com outline dimension pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 48. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model temperature range package description package option ordering qty ADP3208Ajcpz-rl 1 0c to +100c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-1 2,500 1 z = pb-free part. 1.0v boot voltage version on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes witho ut further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specif ications can and do vary in different applications and actu al performance may vary over time. all operating parameters, including ?typicals? must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surg ical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized app lication, buyer shall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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